The present invention relates to a system for automatically verifying a facility adapted to analyze and process a cause of fault, or a similar facility, which is built in a service processor (SVP), and more particularly to an automatic verification system suitable for evaluating a fault cause analyzing/processing facility adapted for a large-scale fault detecting facility in a super computer or similar device.
Conventionally, when a fault detecting facility and a fault cause analyzing/processing facility are examined in a computer system comprised of a host computer and a service processor, a scan-in of error data to the host computer is carried out manually using the function of the service processor to generate a fault. Furthermore, upon generation of the fault, fault data analyzed by means of the fault cause analyzing/processing facility is extracted, for example, by displaying the contents of hardware resources on a console through a framing operation of the service processor, and then such displayed contents are visually verified. A relevant fault generation system is disclosed, for example, in JP-A-60-74049.
However, in the computer system, acceleration logic, as represented by parallel operation logic and pipe line control, is employed in order to realize the speed-up of processings. In this type of computer, a sequenced instruction string is not executed in series, but instead a plurality of instructions are executed in parallel at a point on the time axis in such a manner that during execution of a preceding instruction, execution of the succeeding instruction is started.
Conventionally, in testing the computer system based on the acceleration logic, a fault- is generated manually at a fixed timing and therefore the test can be conducted for only limited types of fault detecting facilities. Further, since upon generation of a fault the fault cause analyzing data is retrieved from analysis data stored in a storage file and visually verified, improvements in test accuracy and efficiency are difficult to achieve. Especially, as far as the large-scale computer having a large-scale fault cause analyzing/processing facility is concerned, a test on the whole of the fault detecting facility and fault cause analyzing/processing facility in the environment of actual operation or execution of the computer system can not be permitted.
More specifically, in spite of the fact that in the system to be tested, actual faults take place at a variety of hardware operation timings while instructions constituting a given instruction string are being organically coupled together and executed in parallel, prior art devices generate a fault at a fixed hardware operation timing by executing only a fixed instruction string comprised of one to several instructions. This means that the environment of fault generation in the prior art differs from that in the actual computer system. For example, even when detecting errors by executing an instruction string in which instructions are organically coupled together to cause execution results of a preceding instruction to affect execution of a subsequently executed instruction (setting up the conflict condition), as in the case where the instruction to be executed is subsequently is rewritten on the basis of the preceding instruction, or execution results of the preceding instruction are used for the subsequently executed instruction, the prior art simply determines, in a single definite way, the organic coupling of individual instructions constituting the instruction string. More damagingly, the prior art has difficulties in preparing the instruction string per se standing for a fault generation means. As is clear from the above, the prior art is operable in only the fault generation environment which is different from the actual fault generation environment for the computer system and it disadvantageously fails to accurately verify the fault detecting facility and the fault cause analyzing/processing facility.